1. Field of the Invention
The present invention relates to computer buses, and more particularly to bus utilization in small computer systems.
2. State of the Art
In computer systems, a bus is commonly used to communicate between logical blocks or devices. The devices connect to a common communications medium, such as a set of wires, or printed circuit board traces. The rules that govern the access of devices to the bus and data transfer on the bus constitute the bus protocol. Generally, all devices on a bus must use the same protocol
In a typical bus implementation, a set of traces are embedded in one or more printed circuit boards. Devices connect to the bus through bus transceivers. Devices connected to a bus may all reside on the same primed circuit board. Such an arrangement is typical of small computer systems, i.e., personal computers and computer workstations. Alternatively, devices may reside on separate printed circuit boards and be attached to an electro-mechanical structure that incorporates the physical bus medium through a series of connectors. The physical bus medium, together with the electro-mechanical structure that incorporates it, is called the backplane bus. Such an arrangement is typical of minicomputers and mainframe computers.
A device connected to the bus may be a master, a slave, or both. A master uses the system bus to issue requests for service to one or more slaves. A slave uses the system bus to respond to requests for service from different masters. A device may at one time issue a request for service and at another time respond to a request for service, thereby functioning as eider a master or a slave.
A small computer system may have only a single bus master that, with relatively few exceptions, enjoys unrestricted access to the system bus. Until recent years, most personal computers were of this type. Alternatively, a computer system may have multiple bus masters that compete for access to the system bus through an arbitration process. Minicomputers and mainframe computers have used such a technique for many years. More recently, some personal computers have moved to a centralized bus arbitration scheme that permits other bus masters to take control of the system bus. In a typical PC, for example, bus masters may include a system microprocessor, processor-board DMA channels, and expansion-slot bus master devices. An arbitrating device detects any pending bus-access requests and grants access to one master at a time according to an arbitration scheme.
Conceptually, a typical computer system bus is divided into an address bus, a data bus, and a control bus. A bus transaction is a complete exchange between two bus devices. A bus transaction may have both an address phase during which address information is presented on the address bus and a data phase during which data information is presented on the data bus. Heretofore, any data phase was coordinated with a corresponding address phae. This sometimes is called a "single envelope" transaction. The PCI Bus specification calls for single envelope transactions. In certain other systems, the data phase of a bus transaction may follow the address phase of the same transaction in ordered succession, without any other data phase of any other bus transaction intervening. In such a case, the system bus is said to be tightly ordered. Small computer systems use, as a general rule, a tightly ordered system bus.
In minicomputer and mainframe computers, on the other hand, buses have often been loosely ordered such that between the address phase of a bus transaction and the corresponding data phase, other data phases of other bus transactions may occur. Alternatively, separate request and response transactions may be defined. For example, a read operation may be split into separate read request and read response transactions, allowing other bus traffic to use the system bus during the actual memory access.
The PowerPC.TM. computer architecture, co-developed by Apple Computer, represents a departure from prior-generation small computer architectures. PowerPC machines currently sold by Apple are based largely on the Motorola MPC601 RISC microprocessor. Other related processors, including the MPC 604, MPC 603, MPC 603e, and MPC 602 are currently available and additional related processors including the MPC 620 will be readily available in the future. The MPC60x family of microprocessors permits separate address bus tenures and data bus tenures, where tenure is defined as the period of bus mastership. In other words, rather than considering the system bus as an indivisible resource and arbitrating for access to the entire bus, the address and data buses are considered as separate resources, and arbitration for access to these two buses may be performed independently. A transaction, or complete exchange between two bus devices, is minimally comprised of an address tenure; one or more data tenures may also be involved in an exchange. There are two kinds of transactions: address/data and address-only.
A tenure consists of three phases: arbitration, transfer, and termination. During termination, a signal occurs that marks the end of the tenure. The same signal is used to acknowledge the transfer of an address or data beat. A beat corresponds generally to a particular state of the address bus or the data bus. Transfers include both single-beat transfers, in which a single piece of data is transferred, and burst data transfers, in which a burst of four data beats is transferred.
Referring more particularly to FIG. 1, note that the address and data tenures are distinct from one another and that both consist of three phases--arbitration, transfer, and termination. FIG. 1 shows a data transfer that consists of a single-beat transfer (up to 64 bits). In a four-beat burst transfer, by contrast, data termination signals are required for each beat of data, but re-arbitration is not required. Having independent address and data tenures allows address pipelining (indicated in FIG. 1 by the fact that the data tenure begins before the address tenure ends) and split-bus transactions to be implemented at the system level. Address pipelining allows new address bus transactions to begin before the current data bus transaction has finished by overlapping the data bus tenure associated with a previous address bus tenure with one or more successive address tenures. Split-bus transaction capability allows the address bus and data bus to have different masters at the same time.
For clarity, the basic functions of address and data tenures will be discussed in somewhat greater detail.
In the case: of address tenure, during address arbitration, address bus arbitration signals are used to gain mastership of the address bus. Assuming the CPU to be the bus master, it then transfers the address on the address bus during the address transfer phase. The address signals, together with certain transfer attribute signals discussed in greater detail hereinafter, control the address transfer. After the address transfer phase, the system uses the address termination phase to signal that the address tenure is complete or that it must be repeated.
In the case of data tenure, during address arbitration, the CPU arbitrates for mastership of the data bus. After the CPU is the bus master, during the data transfer phase, it samples the data bus for read operations or drives the data bus for write operations. Data termination signals occur in the data termination phase. Data termination signals are required after each data beat in a data transfer. In a single-beat-transaction, the data termination signals also indicates the end of the tenure, while in burst accesses, the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat.
Address-only transfers use only the address bus, with no data transfer involved. This feature is particularly useful in multi-master and multiprocessor environments, where external control of on-chip primary caches and TLB (translation look-aside buffer) entries is desirable. Additionally, the MPC60x provides a retry capability that supports an efficient "snooping" protocol for systems with multiple memory systems (including caches) that must remain coherent.
Pipelining and split-bus transactions, while they do not inherently reduce memory latency, can greatly improve effective bus-memory throughput. The MPC60x bus protocol does not constrain the maximum number of levels of pipelining that can occur on the bus between multiple masters. In a system in which multiple devices must compete for the system bus, external arbitration is required. The external arbiter must control the pipeline depth and synchronization between masters and slaves.
In a traditional pipelined implementation, data bus tenures are kept in strict order with respect to address tenures. However, external hardware can further decouple the address and data buses, allowing the data tenures to occur out of order with respect to the address tenures. Such decoupling requires some form of system tag to associate the out-of-order data transaction with the proper originating address transaction. It has been proposed that individual bus requests and data bus grants from each processor may be used by the system to implement tags to support interprocessor, out-of-order transactions. (PowerPC 601 RISC Microprocessor User's Manual, Section 9.2.2, Address Pipelining and Split-Bus Transactions, Motorola Inc., 1993.) No such facility is defined, however, for the MPC601 interface.